|
Number of Channels |
: Six, through six SMA connectors |
|
Input Voltage |
: 2.2 Vpp |
|
Sampling Frequency |
: 60 MHz |
|
Down Sampling Frequency |
: 10 & 5 MHz |
|
DC offset |
: Correction for inputs |
|
ENOB specification |
: 12 bit |
|
Data transfer |
: Either through VME, DSP link ports
or FPGA link port. |
|
Data format |
: Two adjacent channels clubbed and
stored in the FIFO |
|
|
|
DSP |
: ADSP21060 |
|
Operating Frequency |
: 40 MHz |
|
DSP JTAG port |
: On front panel |
|
Booting options |
: FPROM and link port (jumper
selectable) |
|
FIFO |
: Three 16K x 36. |
|
SRAM |
: 64K x 32 |
|
EPROM |
: 512K x 8 for booting |
|
UART |
: Industry standard 16C550 |
|
Link port termination |
: Onto 120 pin high density
connector on facia panel |
|
FIFO depth interrupt |
: Programmable |
|
Front Panel LED indication |
: Two LEDs, DSP flags indication |
|
|
|
VME32 slave standard |
: Support for A32, D32. |
|
Interface |
: Access to FIFOs, SRAM & DSP |
|
Interrupt |
: Configurable |
|
Interrupt sources |
: FIFO full, half full, programmable
empty and DSP flag |
|
|
|
Board size |
: Double EURO (160 mm X 233.35 mm) |
|
Operating Temperature |
: - 20 to +55 C |
|
Storage Temperature |
: - 20 to +70 C |